Source synchronous communication standards are important to enable high-speed data transfer between devices. Board skews and delay variation make it challenging to complete a synchronous transfer with a single central board clock or even a single clock forwarded with a large number of data bits. Consequently, typically a large data bus is divided into groups of bits and a clock or strobe associated with each group of bits is forwarded along with the respective data. An assumption is made that any board skew or delay variation will affect both the clock or strobe and data bits in each group such that the clock or strobe can be reliably used to capture the respective data.
There are a variety of source synchronous memory standards that are in use today. Some of these standards include reduced latency dynamic random access memory (RLDRAM), quad data rate (QDR), and double data rate (DDR). While these standards are similar in many respects, the standards do differ in other respects. For example, QDR and RLDRAM memory devices send back free-running clocks (CQ and QK respectively) to external memory interfaces. DDR memory devices, on the other hand, only toggle a strobe (DQS) to external memory interfaces when data is being sent from the memory, otherwise, the strobe is tri-stated.
When designing an external memory interface to be implemented on an integrated circuit such as an FPGA, designers encounter the challenge of providing a design that supports multiple memory interface standards without requiring a large amount of changes. Designers are also challenged with minimizing the amount of command, read, and write data path latencies which can negatively impact system performance, while facilitating robust timing closure within the integrated circuit.